The present invention relates to a semiconductor storage device and a method of producing same, and more particularly, to a semiconductor storage device having a ferroelectric capacitor as a charge storage capacitor and a method of producing such a device.
Recently, research and development of nonvolatile semiconductor storage devices using a ferroelectric has been energetically made, and some of them have been brought into practice. The conventionally used planar memory cell structure, however, does not serve to increase the integrated density and storage capacity because the cell size of the planar structure is as large as about 100 xcexcm2. In contrast, the stacked structure is suitable for increasing the storage capacity. The stacked structure is a structure in which a ferroelectric capacitor is formed above a source or a drain of a selection transistor via a conductive plug made of, e.g., polysilicon doped with impurities.
In the stacked structure, a capacitor lower electrode is formed on or above the plug of, for example, polysilicon. As an electrode material, a precious metal such as platinum (Pt) is normally used in ferroelectric capacitors. If such a metal is deposited directly on silicon, however, a silicide formation reaction takes place between those materials at relatively low temperatures, which results in poor conduction at the interface between the lower electrode and the conductive plug, and hillocks on a film surface. Conventionally, in order to suppress these phenomena, a barrier metal formed of, for example, titanium nitride (TiN), nitride of an alloy of tantalum and silicon (TaSiN), etc. is provided between the polysilicon plug and the lower electrode.
Those nitrides can suppress the silicide formation reaction between the polysilicon plug and the lower electrode. However, when the lower electrode is formed of Pt, which is very permeable to oxygen, a surface of the barrier metal gets oxidized during a heat treatment performed in an oxygen ambient for crystallization of the ferroelectric. The oxidation of the barrier metal also invites hillocks and film detachment between the lower electrode and the barrier metal. To prevent such a disadvantage, iridium (Ir) having a low permeability to oxygen is often used as a lower electrode material to thereby realize a ferroelectric capacitor having a high resistance to oxidation.
In an ordinary device fabrication process, a barrier metal material, a lower electrode material, a ferroelectric material and an upper electrode material are stacked in this order and then, these materials are subjected to an etching process in the reverse order to thereby form a ferroelectric capacitor including the upper electrode, ferroelectric film and lower electrode, and a barrier metal. After that, a heat treatment process is performed to recover the ferroelectric film. During the etching process and the heat treatment process, however, the following problems take place.
When etching Pt and Ir by a dry etching technique, there occurs etch residue on side surfaces of a resulting pattern and a resist. Etching the barrier metal material without removing such etch residue on the pattern and/or the resist results in change of the pattern size, or shift of the pattern outline. This makes it difficult to form the barrier metal material into a desired shape and also causes a short circuit between the upper and lower electrodes.
If etch residue newly occurs during the etching of the barrier metal material as well, so that the new etch residue is cumulated on the previous etch residue, it is very difficult to remove the cumulative etch residue. In order to prevent cumulation of the etch residue from occurring, it is necessary to stop etching at an interface between the lower electrode material and the barrier metal material, remove the etch residue on the lower electrode, and then start etching the barrier metal material. In most cases, however, it is very difficult to stop the etching at the interface between the lower electrode and the barrier metal material because the etching selection ratio of the lower electrode to the barrier metal is small.
There is another problem. When a ferroelectric material is incorporated in an integrated circuit, the ferroelectric material is subjected to various fabrication processes. Specifically, in the process of forming a ferroelectric capacitor, the ferroelectric material is directly subjected to a dry etching process and a treatment using a chemical liquid. This does damage to the capacitor. Recovery from the damage requires a heat treatment preferably at a temperature as high as 700xc2x0 C. and in an oxygen ambient.
After the capacitor is formed, more specifically, immediately after the lower electrode and the barrier metal are completed through the processing of the lower electrode material and the barrier metal material, side surfaces of the barrier metal are exposed or not covered with any film. If the heat treatment is performed in the oxygen ambient in such a state, the oxidation reaction will proceed in the barrier metal starting from its side surfaces, resulting in the poor conduction due to an increased resistance, development of hillocks, and film detachment. To avoid such disadvantages, conventionally, the heat treatment after the formation of the lower electrode and barrier metal has been performed in an ambient containing no oxygen, such as a nitrogen ambient.
In addition, if a further heat treatment is performed in the oxygen ambient in a process after an interlayer dielectric has been formed over the ferroelectric capacitor, oxygen tends to diffuse through the interlayer dielectric formed of, for example, NSG (Non-doped Silicate Glass) into the barrier metal, so that the barrier metal is oxidized. For this reason, it is difficult to perform a high-temperature heat treatment in the oxygen ambient after the lower electrode and the barrier metal have been formed, which means that it is difficult to recover the characteristic of the ferroelectric capacitor.
Accordingly, an object of the present invention is to provide a semiconductor storage device having a structure that allows the barrier metal to be prevented from oxidation during a high-temperature heat treatment even in an oxygen ambient in the process of producing the device, and to provide a method of producing such a semiconductor storage device.
Another object of the present invention is to provide a semiconductor storage device with a structure which can solve the above etch residue-related problems, and also to provide a method of producing such a semiconductor storage device.
According to an aspect of the present invention, in a semiconductor storage device comprising a MOS transistor formed on a semiconductor substrate, and a capacitor having a lower electrode, an upper electrode, and a dielectric between the lower and upper electrodes, the lower electrode of the capacitor being electrically connected with a source/drain region of the MOS transistor through a contact plug and a barrier metal provided on or above the contact plug, an improvement is characterized in that:
an anti-oxygen-permeation film is formed on entire side surfaces of the barrier metal; and
the lower electrode covers at least an entire upper surface of the barrier metal.
The dielectric may be a ferroelectric.
With the above arrangement, due to the presence of the anti-oxygen-permeation film on the entire side surfaces of the barrier metal, the barrier metal is prevented from being oxidized during a heat treatment which is performed in an oxygen ambient for recovery of the dielectric, especially, of a ferroelectric in the process of producing the storage device. Therefore, the semiconductor storage device is allowed to have a good dielectric (especially ferroelectric) film characteristic.
This storage device can be produced, for example, by a method according to another aspect of the present invention, which comprises the steps of:
depositing a first interlayer dielectric over a semiconductor substrate formed with a MOS transistor, and then forming in the first interlayer dielectric a contact hole leading to a source/drain region of the MOS transistor, and filling the contact hole with a conductive material to thereby form a contact plug electrically connected with the source/drain region;
depositing a barrier metal material over the first interlayer dielectric and the contact plug, and patterning the barrier metal material into a barrier metal which is positioned on or above the contact plug so as to be electrically connected with the contact plug;
depositing an anti-oxygen-permeation film over the barrier metal and the first interlayer dielectric such that a top surface of the anti-oxygen-permeation film on the first interlayer dielectric is at a level higher than a top surface of the barrier metal, and then abrading the anti-oxygen-permeation film by a chemical mechanical polishing technique until the top surface of the barrier metal is exposed;
depositing a lower electrode material, a dielectric material and an upper electrode material in this order on the anti-oxygen-permeation film and the barrier metal, and patterning the upper electrode material, the dielectric material, and the lower electrode material in this order into an upper electrode, a dielectric, and a lower electrode such that the lower electrode covers at least the entire upper surface of the barrier metal, whereby a capacitor associated with the MOS transistor is formed;
depositing a second interlayer dielectric in such a manner that the capacitor is entirely covered with the second interlayer dielectric, and then, forming in the second interlayer dielectric a contact hole leading to the upper electrode; and
performing a heat treatment in an oxygen ambient to recover film quality of the dielectric of the capacitor.
In one embodiment, the anti-oxygen-permeation film is generally L-shaped in section and an insulating film is formed on side surfaces of the anti-oxygen-permeation film, and the insulating film has a film stress smaller than a film stress of the anti-oxygen-permeation film or has a film stress acting in a direction opposite to a direction in which the film stress of the anti-oxygen-permeation film acts.
The semiconductor storage device according to this embodiment can be fabricated by, for example, of a method according to still another aspect of the present invention, which comprises the steps of:
depositing a first interlayer dielectric over a semiconductor substrate formed with a MOS transistor, and then forming in the first interlayer dielectric a contact hole leading to a source/drain region of the MOS transistor, and filling the contact hole with a conductive material to thereby form a contact plug electrically connected with the source/drain region;
depositing a barrier metal material over the first interlayer dielectric and the contact plug, and patterning the barrier metal material into a barrier metal which is positioned on or above the contact plug so as to be electrically connected with the contact plug;
depositing an anti-oxygen-permeation film over the barrier metal and the first interlayer dielectric such that a top surface of the anti-oxygen-permeation film on the first interlayer dielectric is at a level lower than a top surface of the barrier metal, and then depositing an insulating film over the anti-oxygen-permeation film such that a top surface of the insulating film above the first interlayer dielectric is at a level higher than the top surface of the barrier metal, the insulating film being formed of a material having a film stress smaller than a film stress of the anti-oxygen-permeation film or a film stress acting in a direction opposite to a direction in which the film stress of the anti-oxygen-permeation film acts;
abrading the insulating film and the anti-oxygen-permeation film by a chemical mechanical polishing technique until the top surface of the barrier metal is exposed;
depositing a lower electrode material, a dielectric material and an upper electrode material in this order on the insulating film, the anti-oxygen-permeation film and the barrier metal, and patterning the upper electrode material, the dielectric material, and the lower electrode material in this order into an upper electrode, a dielectric, and a lower electrode such that the lower electrode covers at least the entire upper surface of the barrier metal, whereby a capacitor associated with the MOS transistor is formed;
depositing a second interlayer dielectric in such a manner that the capacitor is entirely covered with the second interlayer dielectric, and then, forming in the second interlayer dielectric a contact hole leading to the upper electrode; and
performing a heat treatment in an oxygen ambient to recover film quality of the dielectric of the capacitor.
In one embodiment, the anti-oxygen-permeation film is formed of a material same as a material of the lower electrode so that the anti-oxygen-permeation film and the lower electrode are unified.
Due to the unified structure of the anti-oxygen-permeation film and the lower electrode, namely, a one-piece structure, the semiconductor storage device of this embodiment can be fabricated with less process steps, compared with a case that the anti-oxygen-permeation film and the lower electrode are formed of different materials.
The semiconductor storage device according to this embodiment can be produced by, for example, of a method according to a further aspect of the present invention, which comprises the steps of:
depositing a first interlayer dielectric over a semiconductor substrate formed with a MOS transistor, and then forming in the first interlayer dielectric a contact hole leading to a source/drain region of the MOS transistor, and filling the contact hole with a conductive material to thereby form a contact plug electrically connected with the source/drain region;
depositing a barrier metal material over the first interlayer dielectric and the contact plug, and patterning the barrier metal material into a barrier metal which is positioned on or above the contact plug so as to be electrically connected with the contact plug;
depositing a lower electrode material over the barrier metal and the first interlayer dielectric such that a top surface of the lower electrode material on the first interlayer dielectric is at a level higher than a top surface of the barrier metal, and then planarizing the lower electrode material;
depositing a dielectric material and an upper electrode material in this order on the planarized lower electrode material, and patterning the upper electrode material, the dielectric material, and the lower electrode material in this order into an upper electrode, a dielectric, and a lower electrode such that the lower electrode covers the entire upper surface and entire side surfaces of the barrier metal, whereby a capacitor associated with the MOS transistor is formed;
depositing a second interlayer dielectric in such a manner that the capacitor is entirely covered with the second interlayer dielectric, and then, forming in the second interlayer dielectric a contact hole leading to the upper electrode; and
performing a heat treatment in an oxygen ambient to recover film quality of the dielectric of the capacitor.
With use of any of the above methods, when the lower electrode material is etched for patterning, the barrier metal has already been completed and its side surfaces are covered with the anti-oxygen-permeation film (or the lower electrode material). Therefore, it is possible to solve the problems caused by etch residue, such as change in the pattern size, a short circuit between the upper and lower electrodes.
With use of any of the above methods, because the lower electrode material and the barrier metal material are etched at different steps for patterning, it is easy to remove etch residue, unlike the conventional method in which the lower electrode material and the barrier metal material are continuously etched. Therefore, it is possible to suppress the etch residue-related problems such as change in the pattern size, a short circuit between the upper and lower electrodes, etc.
Other objects, features and advantages of the present invention will be obvious from the following description.